Post by labolas on Jun 18, 2022 23:50:53 GMT
There are various strategies used by verification engineers to achieve the goal. Formal verification is a general term for a set of methods for determining the correct behavior of hardware or software, as opposed to dynamic verification methods such as simulation.
As the size of the projects increased, and with it the simulation time, the validation teams looked for ways to reduce the number of vectors needed to validate the system to an acceptable level of coverage. Formal verification is potentially very fast because it does not need to evaluate every possible state to demonstrate that a given piece of logic matches a set of properties under all conditions.
As the size of the projects increased, and with it the simulation time, the validation teams looked for ways to reduce the number of vectors needed to validate the system to an acceptable level of coverage. Formal verification is potentially very fast because it does not need to evaluate every possible state to demonstrate that a given piece of logic matches a set of properties under all conditions.